An adapted BIOS saves power in existing designs
Low power consumption and high performance computing capabilities are conflicting parameters in a computer board design. Processors, as Intel Atom, have introduced new process technologies and clever processor functions to achieve more with less power. Switching between heavy processing and inactive states is immediate to minimize power consumption.
Similar functionality can be achieved on a platform based on Celeron M/Pentium M family processors and 855GME embedded chipsets using an adapted embedded BIOS and hardware initiated System Management Interrupts, SMI. Powerful performance in combination with additional low power characteristics is achieved to an extent that otherwise only contemporary ultra mobile processor platforms allow.
The following fictitious example is based on experiences from an actual development project using the Hectronic H6036, a PC/104 computer board with an Intel Celeron M, ULV processor running at 1GHz clock rate and the 855GME embedded chipset.We assume that data will be collected and processed in the field. The application needs to be battery operated. The application switches between heavy data processing and periods of waiting for additional data to collect and process.
Complementary computer boards
A dual computer board solution improves the relationship between power consumption and processing capacity. A low-end microcontroller is running continuously. The Celeron M processor processes data, typically in less than a second, and then enters Suspend to RAM, STR. In this state only the RAM memory and selected parts of the chipset consume power.
A possibility would be to let the Linux OS control STR entry and exit. Every entry to STR and exit from STR would then last for a long period of time compared to the time used for data processing, resulting in increased power consumption.An adapted embedded BIOS and SMI, initiated by hardware, would perform the same actions but significantly faster which, results in substantially decreased power consumption and increased battery life.
Setting up the chipset
Data from the sensors are stored in the microcontroller’s FIFO. At the same time the H6036 computer board with Linux is in micro-sleep. A General Purpose I/O, GPIO port is pulled high by the microcontroller when the FIFO is full to wake the H6036 board from micro-sleep.
The embedded BIOS adaptations made by Hectronic include functions to set up the 855GME chipset to trigger a wake event from a positive flank on the GPIO port. The H6036 board exits STR from the wake event. The procedure is similar to a reset but a large part of the code usually run by the BIOS on a reset is excluded and makes STR exit significantly faster.
Entering Suspend to RAM
A negative flank on the GPIO port triggers an SMI in the chipset. In an embedded PC there are numerous SMI generated under normal operation. The embedded BIOS dispatcher decides what code to execute on each SMI. The embedded BIOS dispatcher points out the code to enter STR in this case.
Data in the hardware registers are saved in RAM. Finally the STR entry is achieved when the BIOS writes to a chipset register. The Celeron M processor stops and Linux is brought from micro-sleep to a complete execution halt.
In the example application, to collect and process data in the field, there may be long periods of time before the sensors detect signals. Detecting and collecting data requires low computing power but extended endurance. Using a microcontroller for these tasks prolongs the battery life.
When enough data is collected to justify processing powerful processing capacity is needed. Celeron M at 1 GHz is powerful enough without raising the power consumption unnecessarily. The adapted BIOS controls STR entry and exit.
The alternative using Linux to handle STR entry and exit would lead to procedures of a couple of seconds each. In an application, where the actual processing of data takes 1 second, the procedure as a whole would last about 5 seconds. STR entry and exit would take longer time than the processing itself. That is waste of power and battery life.
The STR entry and exit procedure described in this article is about 0.7 seconds long in all. For the procedure as a whole, including STR exit, 1 second of data processing and STR entry, the time is cut to 1.5 seconds. A 7 Watt power consumption for 1,5 seconds instead of 5 seconds may be the difference that makes it possible to develop a battery powered application, for field use, with enough processing power.